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Optimal clock period for synthesized data paths
For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform ...
FAST: FPGA targeted RTL structure synthesis technique
Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or ...