Now showing items 1-5 of 5
Optimal clock period for synthesized data paths
For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform ...
FAST: FPGA targeted RTL structure synthesis technique
Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or ...
Data path synthesis with global time constraint
This paper presents an algorithm and its implementation for performing scheduling and operator allocation for data path synthesis. The main advantage of this approach is that it is capable of handling global time constraint ...
Speeding up program execution using reconfigurable hardware and a hardware function library
This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a ...
SYMCAD: synthesis of microprogrammed control for automated VLSI design
The paper discusses a software package named SYMCAD, a retargetable microcode synthesizer which forms part of a microprogrammed control synthesis in the VLSI CAD system IDEAS (Integrated Design Automation System). The ...