## Search

Now showing items 1-10 of 35

#### On-chip signature checking for embedded memories

(1998)

The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low ...

#### Efficient implementation of multiple on-chip signature checking

(1997)

Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection ...

#### A scheme for multiple on-chip signature checking for embedded SRAMs

(1997)

Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results ...

#### Star-Graph based multistage interconnection network for ATM switch fabric

(1994)

This paper considers a multistage interconnection network based on the Indirect Star Graph topology as a candidate for an ATM (Asynchronous Transfer Mode) switch fabric. We consider both buffered and unbuffered versions ...

#### Faster fault simulation through distributed computing

(1997)

n this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel ...

#### Simulated annealing for target-oriented partial scan

(1994)

In this paper, we describe algorithms based on simulated annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximise the coverage of faults that are aborted ...

#### Adaptive routing in k-ary n-cubes using incomplete diagnostic information

(1997)

In this paper, we present a fault-tolerant routing algorithm for k-ary n-cube interconnection networks which have become
increasingly popular for the construction of massively parallel computers. The k-ary n-cube is a ...

#### Fault-tolerant routing in multiply twisted cube topology

(1996)

In an attempt to improve the communication diameter of the hypercube interconnection network,variations of the hypercube topology called the twisted cubes have been proposed in the literature.among these,the multiply twisted ...

#### Parallelization of symmetry detection algorithms on a network of workstations

(1997)

Detection of spatial symmetry is useful in several computer vision applications. Due to the real-time nature of the applications, it is
important that symmetry detection algorithms be computationally efficient. Sequential ...

#### Heuristic and Neural Algorithms for Mapping Tasks to a Reconfigurable Array

(1995)

We consider the problem of mapping tasks onto processors in a reconfigurable array architecture. We assume a directed acyclic task graph as input. The node weights in the task graph represent their computational requirement; ...