Now showing items 1-14 of 14

  • ASIP design methodologies: survey and issues 

    Jain, M K; Balakrishnan, M; A Kumar (2001)
    Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the ...
  • Data path synthesis with global time constraint 

    Nedungadi, P P; Balakrishnan, M; A Kumar (1992)
    This paper presents an algorithm and its implementation for performing scheduling and operator allocation for data path synthesis. The main advantage of this approach is that it is capable of handling global time constraint ...
  • Efficient implementation of multiple on-chip signature checking 

    Abdulla, M F; Ravikumar, C P; A Kumar (1997)
    Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection ...
  • Exploring storage organization in ASIP synthesis 

    Jain, M K; Balakrishnan, M; A Kumar (2003)
    Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application ...
  • FAST: FPGA targeted RTL structure synthesis technique 

    Naseer, A R; Balakrishnan, M; A Kumar (1994)
    Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or ...
  • Hybrid Multi-FPGA board evaluation by limiting multi-hop routing 

    Jain, S C; A Kumar; S Kumar (2002)
    Multi-FPGA Boards (MFBs) have been in use for more than a decade for emulation of the digital circuits in many applications. Key feature of an MFB architecture is its inter-FPGA connections. There are two types of inter-FPGA ...
  • Interface synthesis: issues and approaches 

    Rajawat, A; Balakrishnan, M; A Kumar (2000)
    With increasing complexity of electronic systems, automation tools are dominating the design activities. Though there has been marked progress towards hardware synthesis and software synthesis independently, interface ...
  • A new divide and conquer method for achieving high speed division in hardware 

    Mohan, M; Rohini, K; A Kumar; Balakrishnan, M (2002)
    Presents a new method of performing division in hardware and explores different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the dividend, performing division ...
  • A new performance evaluation approach for system level design space exploration 

    Joshi, C P; A Kumar; Balakrishnan, M (2002)
    Application specific systems have potential for customization of design with a view to achieve a better cost-performance-power trade-off. Such customization requires extensive design space exploration. In this paper, we ...
  • On-chip signature checking for embedded memories 

    Abdulla, M F; Ravikumar, C P; A Kumar (1998)
    The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low ...
  • Optimal clock period for synthesized data paths 

    Naseer, A R; Balakrishnan, M; A Kumar (1997)
    For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform ...
  • A scheme for multiple on-chip signature checking for embedded SRAMs 

    Abdulla, M F; Ravikumar, C P; A Kumar (1997)
    Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results ...
  • SoC synthesis with automatic hardware-software interface generation 

    Singh, A; Chhabra, A; Gangwar, A; Dwivedi, B K; Balakrishnan, M; A Kumar (2003)
    Design of efficient system-on-chips (SoCs) requires thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as ...
  • Speeding up program execution using reconfigurable hardware and a hardware function library 

    Jain, S; Balakrishnan, M; A Kumar; Kumar, S (1998)
    This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a ...