Now showing items 1-16 of 16

  • ASIP design methodologies: survey and issues 

    Jain, M K; Balakrishnan, M; A Kumar (2001)
    Interest in synthesis of Application Specific Instruction Processors or ASIPs has increased considerably and a number of methodologies have been proposed in the last decade. This paper attempts to survey the state of the ...
  • Data path synthesis with global time constraint 

    Nedungadi, P P; Balakrishnan, M; A Kumar (1992)
    This paper presents an algorithm and its implementation for performing scheduling and operator allocation for data path synthesis. The main advantage of this approach is that it is capable of handling global time constraint ...
  • Evaluating register file size in ASIP design 

    Jain, Manoj Kumar; Wehmeyer, Lars; Steinke, Stefan; Marwedel, Peter; Balakrishnan, M (2001)
    Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding ...
  • Exploring storage organization in ASIP synthesis 

    Jain, M K; Balakrishnan, M; A Kumar (2003)
    Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application ...
  • FAST: FPGA targeted RTL structure synthesis technique 

    Naseer, A R; Balakrishnan, M; A Kumar (1994)
    Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or ...
  • Interface synthesis: issues and approaches 

    Rajawat, A; Balakrishnan, M; A Kumar (2000)
    With increasing complexity of electronic systems, automation tools are dominating the design activities. Though there has been marked progress towards hardware synthesis and software synthesis independently, interface ...
  • A new divide and conquer method for achieving high speed division in hardware 

    Mohan, M; Rohini, K; A Kumar; Balakrishnan, M (2002)
    Presents a new method of performing division in hardware and explores different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the dividend, performing division ...
  • A new performance evaluation approach for system level design space exploration 

    Joshi, C P; A Kumar; Balakrishnan, M (2002)
    Application specific systems have potential for customization of design with a view to achieve a better cost-performance-power trade-off. Such customization requires extensive design space exploration. In this paper, we ...
  • A novel reconfigurable co-processor architecture 

    Aggarwal, G; Thaper, N; Aggarwal, K; Balakrishnan, M; S Kumar (1997)
    Back-end processors have been conventionally used for speeding up of only a specific set of compute intensive functions. Such co-processors are, generally, “hardwired” and cannot be used for a new function. In this paper, ...
  • Optimal clock period for synthesized data paths 

    Naseer, A R; Balakrishnan, M; A Kumar (1997)
    For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform ...
  • Optimal hardware/software partitioning for concurrent specification using dynamic programming 

    Shrivastava, A; H Kumar; Kapoor, S; S Kumar; Balakrishnan, M (2000)
    An important aspect of hardware-software co-design is partitioning of tasks to be scheduled on the hardware and software resources. Existing approaches separate partitioning and scheduling in two steps. Since partitioning ...
  • SoC synthesis with automatic hardware-software interface generation 

    Singh, A; Chhabra, A; Gangwar, A; Dwivedi, B K; Balakrishnan, M; A Kumar (2003)
    Design of efficient system-on-chips (SoCs) requires thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as ...
  • A specialized graduate program in VLSI design: a success story 

    Balakrishnan, M (2000)
    This paper describes the recently started interdisciplinary, industry-sponsored graduate program entitled VLSI Design, Tools & Technology at IIT Delhi. In a short span of 5 years, the program has achieved considerable ...
  • Speeding up program execution using reconfigurable hardware and a hardware function library 

    Jain, S; Balakrishnan, M; A Kumar; Kumar, S (1998)
    This paper describes a co-design environment which follows a new approach for speeding up compute intensive applications. The environment consists of three major components. First, a target architecture consisting of a ...
  • Synthesis of application specific multiprocessor architectures for process networks 

    Dwivedi, Basant Kumar; Anshul Kumar; Balakrishnan, M (2004)
    In this paper, we address the problem of synthesis of application specific multiprocessor SoC architectures for process networks of streaming applications. An application is modeled as Kahn Process Network (KPN) which makes ...
  • A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units 

    Middha, Bhuvan; Raj, Varun; Gangwar, Anup; Kumar, Anshul; Balakrishnan, M; Ienne, Paolo (2002)
    It is widely accepted that use of an Application Specific Instruction Set Processor (ASIP) in an embedded system can provide a solution which is much more flexible than ASICs and much more efficient than standard processors ...