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On-chip signature checking for embedded memories
(1998)
The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low ...
Interface synthesis: issues and approaches
(2000)
With increasing complexity of electronic systems, automation tools are dominating the design activities. Though there has been marked progress towards hardware synthesis and software synthesis independently, interface ...
Optimal clock period for synthesized data paths
(1997)
For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform ...
Efficient implementation of multiple on-chip signature checking
(1997)
Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection ...
FAST: FPGA targeted RTL structure synthesis technique
(1994)
Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or ...
Data path synthesis with global time constraint
(1992)
This paper presents an algorithm and its implementation for performing scheduling and operator allocation for data path synthesis. The main advantage of this approach is that it is capable of handling global time constraint ...
A scheme for multiple on-chip signature checking for embedded SRAMs
(1997)
Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results ...
Hybrid Multi-FPGA board evaluation by limiting multi-hop routing
(2002)
Multi-FPGA Boards (MFBs) have been in use for more than a decade for emulation of the digital circuits in many applications. Key feature of an MFB architecture is its inter-FPGA connections. There are two types of inter-FPGA ...
A new divide and conquer method for achieving high speed division in hardware
(2002)
Presents a new method of performing division in hardware and explores different ways of implementing it. This method involves computing a preliminary estimate of the quotient by splitting the dividend, performing division ...
A new performance evaluation approach for system level design space exploration
(2002)
Application specific systems have potential for customization of design with a view to achieve a better cost-performance-power trade-off. Such customization requires extensive design space exploration. In this paper, we ...