Now showing items 1-4 of 4
On-chip signature checking for embedded memories
The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low ...
Efficient implementation of multiple on-chip signature checking
Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer from long detection ...
A scheme for multiple on-chip signature checking for embedded SRAMs
Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results ...
A scheme for multiple on-chip signature checking for embedded SRAMS
Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a ...